Multiplexers are used, for example, within a programmable logic device (PLD), such as a field programmable gate array (FPGA) or a complex programmable logic device (CPLD), to provide a portion of a programmable interconnect architecture (e.g., the routing multiplexers). However for a given design, there may be a substantial number of the routing multiplexers that are unused, which may result in a significant amount of current shunted to ground if the routing multiplexer's inverter stage inputs were left to float.
Various conventional approaches are known to drive or latch the inverter stage inputs to a desired logic level. For example, one approach requires that every multiplexer has a multiplexer input selected (i.e., every multiplexer is used, even if its output is not required), with unused multiplexers possibly provided with a supply voltage (Vcc) input signal. However, one drawback with this approach is that the dynamic Icc in the device (e.g., PLD) may be significantly increased, because the unused multiplexer inverters may switch even though their outputs are not needed for the particular design. Furthermore, signal loading, signal fanout, and leakage current issues may be additional drawbacks associated with the unused multiplexers with this approach of holding the unneeded multiplexer in a proper off state via a supplied input signal.
As another example, another conventional approach provides an additional multiplexer input tied to the supply voltage (Vcc) or ground (Vss), which would be selected when the multiplexer is unused. Although there are fewer leakage paths and no fanout issues as compared to the prior approach, this approach however requires an extra fuse (or signal) to control the additional multiplexer input, adds capacitive loading, and requires additional circuitry and silicon area.
As another example, another approach provides an additional transistor to “tie off” a multiplexer inverter stage input to a logical high, while all of the multiplexer inputs are deselected. Although this approach also does not have leakage current or fanout issues, the additional transistor requirement for each multiplexer is a drawback. Furthermore, a corresponding fuse for each multiplexer is required to control the additional transistor or, alternatively, a pulsed control signal may be provided (e.g., a globally-routed signal) to control the additional transistor. However, the pulsed control signal may require a buffering network and may consume a metal track of appreciable width near each multiplexer.
As a result, there is a need for improved multiplexer techniques.